Arachnaut's Lair

Summary of differences in Intel 32-bit and 64-bit run time models

This is a selection of extracts from the Intel microprocessor manual showing the differences between the 32-bit and the 64-bit run time models of current Intel Core computers. In other words, if you have a 64-bit OS and run a 32-bit application on that machine, the machine will run the application in a 32-bit virtual model.

The software operating system may make other virtual changes, that part is not covered, this is just the hardware differences.

You will have to get the manual to read more about this, I just perused the manual and tried to summarize where there were any differences to be found. I may have missed some.

The manual is:

"Intel® 64 and IA-32 Architectures, Software Developer's Manual, December 2011".

Order Number: 325462-041US

Intel® 64 and IA-32 Architectures
Software Developer's Manual

Order Number: 325462-041US

December 2011

2.2.10 Intel® 64 Architecture

Intel 64 architecture increases the linear address space for software to 64 bits
and  supports  physical  address  space  up  to  40  bits.  The  technology also
introduces a new operating mode referred to as IA-32e mode.

IA-32e mode operates in one of  two sub-modes: (1) compatibility mode enables  a
64-bit operating system  to run most  legacy 32-bit software  unmodified, (2) 64
-bit  mode enables  a 64-bit  operating system  to run  applications written  to
access 64-bit address space.

In the 64-bit mode, applications may access:

* 64-bit flat linear addressing
* 8 additional general-purpose registers (GPRs)
* 8 additional registers for streaming SIMD extensions (SSE, SSE2, SSE3 and SSSE3)
* 64-bit-wide GPRs and instruction pointers
* uniform byte-register addressing
* fast interrupt-prioritization mechanism
* a new instruction-pointer relative-addressing mode

An Intel 64 architecture processor  supports existing IA-32 software because  it
is able to run all non-64-bit legacy modes supported by IA-32 architecture. Most
existing IA-32 applications also run in compatibility mode.

3.1.1 Intel® 64 Architecture

{Figure 3-1 and 3-2 compare IA-32 and 64-bit modes, respectively}

Figure 3-1. The 32 bit model.
32-bit model

Figure 3-2. The 64-bit model.
64-bit model

Intel 64 architecture adds IA-32e mode. IA-32e mode has two sub-modes.

These are:

* Compatibility mode (sub-mode of IA-32e mode) - Compatibility mode permits most
legacy 16-bit and 32-bit applications  to run without re-compilation under  a 64
-bit operating system. For brevity, the compatibility sub-mode is referred to as
compatibility  mode  in  IA-32   architecture.  The  execution  environment   of
compatibility mode is the same as described in Section 3.2.

Compatibility mode also supports all of the privilege levels that are  supported
in 64-bit and protected modes. Legacy applications that run in Virtual 8086 mode
or use hardware task management will  not work in this mode. Compatibility  mode
is enabled by the operating system (OS) on a code segment basis. This means that
a single 64-bit OS  can support 64-bit applications  running in 64-bit mode  and
support  legacy  32-bit applications  (not  recompiled for  64-bits)  running in
compatibility mode.

Compatibility mode is similar to 32-bit protected mode. Applications access only
the first 4  GByte of linear-address  space. Compatibility mode  uses 16-bit and
32-  bit  address and  operand  sizes. Like  protected  mode, this  mode  allows
applications to access physical memory greater than 4 GByte using PAE  (Physical
Address Extensions).

* 64-bit mode (sub-mode of IA-32e  mode) - This mode enables a  64-bit operating
system to run  applications written to  access 64-bit linear  address space. For
brevity,  the  64-bit  sub-mode  is   referred  to  as  64-bit  mode   in  IA-32

64-bit mode extends the number  of general purpose registers and  SIMD extension
registers from 8 to  16. General purpose registers  are widened to 64  bits. The
mode  also  introduces  a  new  opcode  prefix  (REX)  to  access  the  register
extensions. See Section 3.2.1 for a detailed description.

64-bit mode  is enabled  by the  operating system  on a  code-segment basis. Its
default address size  is 64 bits  and its default  operand size is  32 bits. The
default operand size  can be overridden  on an instruction-by-instruction  basis
using a REX opcode prefix in conjunction with an operand size override prefix.

REX prefixes allow  a 64-bit operand  to be specified  when operating in  64-bit
mode. By using this mechanism, many existing instructions have been promoted  to
allow the use of 64-bit registers and 64-bit addresses.

5-38 Vol. 1


The following instructions are introduced in 64-bit mode. This mode is a sub-mode of
IA-32e mode

CDQE Convert doubleword to quadword
CMPSQ Compare string operands
CMPXCHG16B Compare RDX:RAX with m128
LODSQ Load qword at address (R)SI into RAX
MOVSQ Move qword from address (R)SI to (R)DI
MOVZX (64-bits) Move doubleword to quadword, zero-extension
STOSQ Store RAX at address RDI
SWAPGS Exchanges current GS base register value with value in MSR address C0000102H
SYSCALL Fast call to privilege level 0 system procedures
SYSRET Return from fast system call


6.2.5 Stack Behavior in 64-Bit Mode
6.3.7 Branch Functions in 64-Bit Mode
6.4.6 Interrupt and Exception Behavior in 64-Bit Mode

7.2 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS IN 64-BIT MODE Exchange Instructions in 64-Bit Mode Type Conversion Instructions in 64-Bit Mode Increment and Decrement Instructions in 64-Bit Mode

7.3.4 Decimal Arithmetic Instructions in 64-Bit Mode

Decimal  arithmetic instructions  are not  supported in  64-bit mode,  They are
either invalid or not encodable. Control Transfer Instructions in 64-Bit Mode Software Interrupt Instructions in 64-bit Mode and Compatibility Mode

In 64-bit mode, the stack size is  8 bytes wide. IRET must pop 8-byte  items off
the stack. SS:RSP pops unconditionally. BOUND is not supported.

In compatibility mode, SS:RSP is popped only if the CPL changes. String Operations in 64-Bit Mode
7.3.11 I/O Instructions in 64-Bit Mode
7.3.14 Flag Control (RFLAG) Instructions in 64-Bit Mode


8.1.1 x87 FPU in 64-Bit Mode and Compatibility Mode

In compatibility mode and 64-bit  mode, x87 FPU instructions function  like they
do  in protected  mode. Memory  operands are  specified using  the ModR/M,   SIB
encoding that is described in Section 3.7.5, "Specifying an Offset."

10.2.1 SSE in 64-Bit Mode and Compatibility Mode

In compatibility mode, SSE extensions  function like they do in  protected mode.
In 64-bit mode,  eight additional XMM  registers are accessible.  Registers XMM8
-XMM15 are accessed by using  REX prefixes. Memory operands are  specified using
the ModR/M, SIB encoding described in Section 3.7.5.

Some SSE instructions may be  used to operate on general-purpose  registers. Use
the REX.W prefix to access 64-bit general-purpose registers. Note that if a  REX
prefix is used when it has no meaning, the prefix is ignored.

12.1.1 SSE3, SSSE3, SSE4 in 64-Bit Mode and Compatibility Mode

In compatibility mode, SSE3, SSSE3, and SSE4 function like they do in  protected
mode. In 64-bit mode, eight  additional XMM registers are accessible.  Registers
XMM8-XMM15 are accessed by using REX prefixes.


SSE4 comprises of two sets of extensions: SSE4.1 and SSE4.2. SSE4.1 is  targeted
to improve  the performance  of media,  imaging, and  3D workloads.  SSE4.1 adds
instructions  that  improve compiler  vectorization  and significantly  increase
support for packed dword computation.  The technology also provides a  hint that
can improve memory throughput when reading from uncacheable WC memory type. AES Data Structure in Intel 64 Architecture

End of document.

Valid HTML 4.01 Transitional